1. Field of the invention
The present invention relates to an integrated circuit device, for details, an integrated circuit device having a plurality of integrated circuit chips having an integrated circuit operated at a specified voltage; and an interposer.
2. Description of the Prior Art
A proposed structure of an integrated circuit device includes
a plurality of flash memory chips having a flash memory. In the proposed structure, the flash memory of the flash memory chips is divided into a plurality of banks and data are read and written from each bank by memory interleaving. Data are read and written in parallel from each flash memory chip (see, for example, Non-Patent Document 1). In this proposed integrated circuit device , this control successively performs high speed read/write operation.Non-Patent Document 1: Chanik Park, Prakash Talawar, Daesik Won, MyungJin Jung, JungBeen Im, Suksan Kim and Youngjoon Choi, ┌A High Performance Controller for NAND Flash-based Solid State Disk (NSSD) ┘, IEEE Non-Volatile Semiconductor Memory Workshop, pp. 17-20, Feb. 2006
In this prior art integrated circuit device, the more flash memories to be read or written are, the larger power consumption is. Control reducing number of operating flash memory chips and making suppress of the consumption power take precedence over high speed transfer of data is generally performed. The number of the operating flash memory chips actually varies by the control. this prior art integrated circuit device, the flash memory regularly has a boost converter supplying high voltage for the write operating required for writing data in the flash memory chips. The boost converter does not boost the voltage properly when the number of the operating flash memory chips, that is, load of the boost converter varies while the boost converter boosts the voltage. For example, controlling a switching element of the boost converter by the signal that has the same on-time as before an increase in the number of the flash memory chips causes an increase in the time required for the voltage to reach the high voltage for write operation when the load of the boost converter is increased by the increase in the number of the operating flash memory chips while the boost converter boosts the voltage. Controlling the switching element of the boost converter by the signal that has the same on-time as before a decrease in the number of the flash memory chips causes earlier output of the high voltage for the write operation than necessary and wastes electric power when the load of the boost converter is decreased by the decrease in the number of the operation flash memory chips while the boost converter boosts the voltage. So it is desired to boost the voltage properly in response to increase and decrease in the number of the operation chips.